The invention relates to a two-line multi-station bus system with a clock wire and a data wire, said system supporting selective slave station addressing by a prevalent master station for thereupon eliciting a bitwise clocked data transfer between said clocking master station and an addressed and clocked slave station. Such a system has been described in EP Patent 51332 and corresponding U.S. Pat. No. 4,689,740 (PHN 9873) to the same assignee as the present application, herein incorporated by reference. The reference describes the so-called I2C system that has been designed predominantly for communicating control signals between integrated circuit chips that are located within a single apparatus such as may be intended for, but not limited to consumer entertainment. I2C has gained status as de facto standard.
The present invention intends to extend the field of use of bus systems that are of comparable structure as, but not necessarily identical to the I2C bus, in particular to such applications where both digital and analog signals occur. One field of application is where a slave station may emit a bit stream that in principle may have an infinite length. A particular example of an analog signal is one wherein a slave station is a smart sensor that when addressed emits a sense signal with an analog amplitude or shape. Analog in this context means multivalued to such extent as the receiver can discriminate, such discrimination being generally equal to the discrimination assigned to a signal by a transmitter, although the granularity applied by the receiver may be coarser.